View SAB9076H_173171.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAB9076H Picture-In-Picture (PIP) controller
Preliminary specification File under Integrated Circuits, IC02 1996 Aug 13
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
FEATURES Display * Twin PIP in interlaced mode at 8-bit resolution * Sub-title mode features built in * Large display fine positioning area, both channels independent * Only 2 Mbit required as external VDRAM (2 x 1 Mbit or 1 x 2 Mbit) * Four 8-bit Analogue Digital Converters (ADCs; > 7-bit performance) with clamp circuit * Most PIP modes handle interlaced pictures without joint line error * Two PLLs which generate the line-locked clocks for the acquisition channels * Display PLL to generate line-locked clock for the display * Three 8-bit Digital Analogue Converters (DACs) * 4 : 1 : 1 data format * Data reduction factors 1 to 1, 1 to 2, 1 to 3 and 1 to 4, horizontal and vertical independent. I2C-bus programmable * Single and double PIP modes can be set * Full field still mode available * Several aspect ratios can be handled * Reduction factors can be set freely * Selection of vertical filtering type * Freeze of live pictures * Fine tuned display position, H (8-bit), V (8-bit), both channels independent * Fine tuned acquisition area, H (4-bit), V (8-bit), both channels independent * Eight main borders, sub-borders and background colours selectable * Border and background brightness adjustable, 30%, 50%, 70% and 100% IRE * Several type of decoder input signals can be set.
SAB9076H
GENERAL DESCRIPTION The SAB9076H is a picture-in-picture controller for NTSC TV-sets. The circuit contains ADCs, reduction circuitry, memory control, display control and DACs. The device inserts one or two live video signals with original or reduced sizes into a live video signal. All video signals are expected to be analog baseband signals. The conversion into the digital environment and back to the analog environment is carried out on chip. Internal clocks are generated by two acquisition PLLs and a display PLL. Due to the two PIP channels and a large external memory a wide range of PIP modes are offered. The emphasis is put on single-PIP, double-PIP, split-screen mode and a many multi-PIP modes.
1996 Aug 13
2
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
QUICK REFERENCE DATA SYMBOL VDD IDD fsys floop tjitter Note PARAMETER supply voltage supply current system frequency PLL loop bandwidth frequency PLL short term stability time PLL damping factor jitter during 1 line (64 s) note 1 CONDITIONS MIN. 4.5 - - 4 - -
SAB9076H
TYP. 5.0 200 27 - - 0.7
MAX. 5.5 - - - 4 -
UNIT V mA MHz kHz ns -
1. The internal system frequency is 1728 times the HSync input frequency for both the Acquisition and Display PLLs. ORDERING INFORMATION TYPE NUMBER SAB9076H Note 1. When using IR reflow soldering it is recommended that the Drypack instructions in the "Quality Reference Handbook" (order number 9398 510 63011) are followed. PACKAGE NAME QFP100(1) DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT317-2
1996 Aug 13
3
handbook, full pagewidth
1996 Aug 13
WE DAVSSA DAVDDA 84 83 CAS DT 47 31 40 32, 34, 36, 38, 39, 37, 35, 33 86 DY DU DV DAVbias DAVrefT 89 DAVrefB 90 88 85 87 23, 25, 27, 29, 30, 28, 26, 24 51, 53, 55, 91 57, 58, 56, 54, 52, 50 92 DAO0 to DAO7 AD0 to AD8 DAVDDD 48 SC DAI0 to DAI7 DAVSSD 69 68 70 67 13 14 49 HORIZONTAL AND VERTICAL FILTER DAC AND BUFFER VDRAM CONTROL AND (RE-) FORMATTING
BLOCK DIAGRAM
MAVSSD
Philips Semiconductors
MAVDDD
RAS SAVSSD SVSSD MAVSSA SAVSSA MVSSD SAVDDD SVDDD MAVDDA SAVDDA MVDDD
3
4
12
11
78
77
SY
71
SU
75
SV
73
SAVbias
76
CLAMP AND ADC
SAVrefT
74
SAVrefB
72
SPHsync LINE MEMORY
79 DISPLAY CONTROL 93 DFB
Picture-In-Picture (PIP) controller
64
SVsync SPVbias
80
PLL AND CLOCK GENERATOR
MY
10
4
HORIZONTAL AND VERTICAL FILTER
MU
6
MV
8
MAVbias
5
CLAMP AND ADC
SAB9076H
LINE MEMORY
7
MAVrefT MAVrefB
9
MPHsync LINE MEMORY I2C-BUS CONTROL
2 PLL AND CLOCK GENERATOR
96 94 95
17
MVsync MPVbias
1
PLL AND CLOCK GENERATOR
DPVbias DVsync DPHsync
100
99
98
97
81
82
66
65
46
45
44
43
42
41
62
61
60 SCL SDA
59
16 MCVSSD A0
15
20 TM0 MCVDDD
21
22 TM2 TM1
19
18 TDCLK TC
63
MGC962
POR DCVDDD DVSSD VDDD SCVDDD SPVSSA DPVDDA MPVSSA DCVSSD DVDDD VSSD SCVSSD SPVDDA DPVSSA MPVDDA
TACLK
Preliminary specification
SAB9076H
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
PINNING SYMBOL MPVbias MPHsync MAVSSD MAVDDD MAVbias MU MAVrefT MV MAVrefB MY MAVDDA MAVSSA MVSSD MVDDD MCVDDD MCVSSD MVsync TDCLK TC TM0 TM1 n.c. DAI0 DAI7 DAI1 DAI6 DAI2 DAI5 DAI3 DAI4 DT DAO0 DAO7 DAO1 DAO6 DAO2 DAO5 DAO3 DAO4 SC 1996 Aug 13 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I/O I I/O I/O I I I I I I I/O I/O I/O I/O I/O I/O I I I I I - I I I I I I I I O O O O O O O O O O TYPE E027 HPP01 E009 E030 E027 E027 E027 E027 E027 E027 E030 E009 E009 E030 E030 E009 HPP01 HPP01 HPP01 HPP01 HPP01 - HPP01 HPP01 HPP01 HPP01 HPP01 HPP01 HPP01 HPP01 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 DESCRIPTION analog bias reference for main channel
SAB9076H
horizontal synchronization input for main channel digital ground for main channel ADCs and PLLs digital positive power supply for main channel ADCs and PLLs analog bias reference input for main channel ADCs analog U input for main channel analog top reference voltage input for main channel ADCs analog V input for main channel analog bottom reference voltage input for main channel ADCs analog Y input for main channel analog positive power supply for main channel ADCs analog ground for main channel ADCs digital ground for main-channel core digital positive power supply for main-channel core digital positive power supply for main-clock buffer digital ground for main-clock buffer vertical synchronization input for main channel test clock input for display test control input test mode 0 input test mode 1 input not connected data bus input from memory; bit 0 data bus input from memory; bit 7 data bus input from memory; bit 1 data bus input from memory; bit 6 data bus input from memory; bit 2 data bus input from memory; bit 5 data bus input from memory; bit 3 data bus input from memory; bit 4 memory data transfer output; active LOW data bus output to memory; bit 0 data bus output to memory; bit 7 data bus output to memory; bit 1 data bus output to memory; bit 6 data bus output to memory; bit 2 data bus output to memory; bit 5 data bus output to memory; bit 3 data bus output to memory; bit 4 memory shift clock output 5
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
SYMBOL DCVSSD DCVDDD DVDDD DVSSD VSSD VDDD WE CAS RAS AD8 AD0 AD7 AD1 AD6 AD2 AD5 AD3 AD4 A0 SCL SDA POR TACLK SVsync SCVSSD SCVDDD SVDDD SVSSD SAVSSA SAVDDA SY SAVrefB SV SAVrefT SU SAVbias SAVDDD SAVSSD SPHsync SPVbias SPVSSA 1996 Aug 13
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O I I I/O I I I I/O I/O I/O I/O I/O I/O I I I I I I/O I/O I/O I I/O I/O
TYPE E009 E030 E030 E009 E009 E030 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 HPF01 HPF01 IOI41 HUP07 HPP01 HPP01 E009 E030 E030 E009 E009 E030 E027 E027 E027 E027 E027 E027 E030 E009 HPP01 E027 E009
DESCRIPTION digital ground for display-clock buffer digital positive power supply for display-clock buffer digital positive power supply for display core digital ground for display core digital ground for peripherals digital positive power supply for peripherals memory write enable output; active LOW memory column address strobe output; active LOW memory row address strobe output; active LOW memory address bus output; bit 8 memory address bus output; bit 0 memory address bus output; bit 7 memory address bus output; bit 1 memory address bus output; bit 6 memory address bus output; bit 2 memory address bus output; bit 5 memory address bus output; bit 3 memory address bus output; bit 4 I2C-bus address 0 selection input shift clock input for I2C-bus shift I2C-bus input data; acknowledge I2C-bus output data power-on reset input test clock input for acquisition vertical synchronization input for sub-channel digital ground for sub-clock buffer digital positive power supply for sub-clock buffer digital positive power supply for sub-channel core digital ground for sub-channel core analog ground for sub-channel ADCs analog positive power supply for sub-channel ADCs analog Y input for sub-channel analog bottom reference input voltage for sub-channel ADCs analog V input for sub-channel analog top reference input voltage for sub-channel ADCs analog U input for sub-channel analog bias reference input/output for sub-channel ADCs digital positive power supply for sub-channel ADCs and PLLs digital ground for sub-channel ADCs and PLLs horizontal synchronization input for sub-channel analog bias reference input/output for sub-channel analog ground for sub-channel PLL 6
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
SYMBOL SPVDDA DAVDDA DAVSSA DAVbias DY DAVrefT DV DAVrefB DU DAVSSD DAVDDD DFB DVsync DPHsync DPVbias DPVSSA DPVDDA MPVDDA MPVSSA Table 1
PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
I/O I/O I/O I/O I O I O I O I/O I/O O I I I/O I/O I/O I/O I/O
TYPE E030 E030 E009 E027 E027 E027 E027 E027 E027 E009 E030 OPF20 HPP01 HPP01 E027 E009 E030 E030 E009
DESCRIPTION analog positive power supply for sub-channel PLL analog positive power supply for DACs analog ground for DACs analog bias voltage reference input for DACs analog Y output of DAC analog top reference input voltage for DACs analog V output of DAC analog bottom reference input voltage for DACs analog U output of DAC digital ground for DACs digital positive power supply for DACs fast blanking control output signal vertical synchronization input for display channel horizontal synchronization input for display PLL analog bias voltage reference input/output for display PLL analog ground for display PLL analog positive power supply for display PLL analog positive power supply for main channel PLL analog ground for main channel PLL
Pin type explanation DESCRIPTION VDD pin; diode to VSS VSS pin; diode to VDD analog input pin; diode to VDD and VSS digital input pin; CMOS levels, diode to VSS digital input pin; CMOS levels, diode to VDD and VSS digital input pin; CMOS levels with hysteresis, pull-up resistor to VDD, diode to VDD and VSS I2C-bus pull-down output stage; CMOS input levels, diode to VSS digital output pin; CMOS levels
PIN TYPE E030 E009 E027 HPF01 HPP01 HUP07 IOI41 OPF20
1996 Aug 13
7
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
100 MPVSSA 99 MPVDDA
92 DAVDDD 91 DAVSSD
98 DPVDDA 97 DPVSSA
83 DAVDDA 82 SPVDDA
96 DPVbias 95 DPHsync
85 DAVbias 84 DAVSSA
89 DAVrefB 88 DV
87 DAVrefT
94 DVsync
handbook, full pagewidth
81 SPVSSA 80 SPVbias 79 SPHsync 78 SAVSSD 77 SAVDDD 76 SAVbias 75 SU 74 SAVrefT 73 SV 72 SAVrefB 71 SY 70 SAVDDA 69 SAVSSA 68 SVSSD 67 SVDDD 66 SCVDDD 65 SCVSSD 64 SVsync 63 TACLK 62 POR 61 SDA 60 SCL 59 A0 58 AD4 57 AD3 56 AD5 55 AD2 54 AD6 53 AD1 52 AD7 51 AD0 AD8 50
MGC963
93 DFB
90 DU
MPVbias MPHsync MAVSSD MAVDDD MAVbias MU MAVrefT MV MAVrefB
1 2 3 4 5 6 7 8 9
MY 10 MAVDDA 11 MAVSSA 12 MVSSD 13 MVDDD 14 MCVDDD 15 MCVSSD 16 MVsync 17 TDCLK 18 TC 19 TM0 20 TM1 21 n.c. 22 DAI0 23 DAI7 24 DAI1 25 DAI6 26 DAI2 27 DAI5 28 DAI3 29 DAI4 30 DT 31 DAO0 32 DAO7 33 DAO1 34 DAO6 35 DAO2 36 DAO5 37 DAO3 38 DAO4 39 SC 40 DCVSSD 41 DCVDDD 42 DVDDD 43 DVSSD 44 VSSD 45 VDDD 46 WE 47 CAS 48 RAS 49
SAB9076H
Fig.2 Pin configuration.
1996 Aug 13
8
86 DY
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
FUNCTIONAL DESCRIPTION Pixel rate The internal chrominance format used is 4 : 1 : 1. It is expected that the bandwidth of the input signals is limited to 4.5 MHz for the Y input and 1.125 MHz for the U/V input. The Y input is sampled with a 1728 x HS (27.0 MHz) clock and is filtered and down sampled to the internal 864 x HS (13.5 MHz) pixel rate. The U and V inputs are multiplexed and sampled with a 432 x HS clock and down sampled to the internal 216 x HS (3.375 MHz) pixel rate. Acquisition area Synchronisation is achieved via the acquisition HSync and Vsync pins. With the acquisition fine positioning added to a system constant the starting point of the acquisition can be controlled. The acquisition area is 672 pixels/line and 228 lines/field for NTSC. Both main and sub-channels are equivalent in handling the data. Table 2 PIP sizes H/1 672 - H/2 336 - H/3 224 - H/4 168 - V/1 - 228 V/2 - 114 Display mode
SAB9076H
The internal display pixel rate is 864 x DPHsync which is 13.5 MHz. This pixel rate is up sampled by interpolation to 1728 x DPHsync before the DAC stage. Display area The display background is an area of 696 pixels and 238 lines. This can be put on/off by the BGON bit independent of the PIPON bit. This area can be moved by the display background fine positioning (BGHFP and BGVFP registers). Its colour is determined by the BGCOL and BGBRT registers. Within this area PIPs are defined dependent on the PIP mode. The PIP sizes are determined by the display reduction factors as is shown in Table 2. The display fine positioning determines the location of the PIPs with respect to the background. Sub-channel and main channel both have their independent PIP size and location control, which is shown in Fig.3.
REDUCTION Pixels Lines
V/3 - 76
V/4 - 57
1996 Aug 13
9
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
handbook, full pagewidth
BGHFP
BGVFP SAVFP
SAHFP MAVFP MAHFP
SUB CHANNEL
MAIN CHANNEL 238 lines
696 pixels
MGC964
Fig.3 Display fine positioning.
PIP modes The two independent acquisition channels can be controlled independently on the display side. A wide variety of modes is possible but a subset of 7 modes is fixed and can be set easily by the I2C-bus. An overview of the preconditioned modes is given in Table 3. For all PIP modes the main and sub-display fine positioning must be set to obtain a display configuration. DATA TRANSFER The internal data path has an 8-bit resolution and 4 : 1 : 1 data format. The communication to the external VDRAM takes place at 864 x Hsync (both display and acquisition).
Approximately 800 8-bit words can be fetched from the external VDRAM in one display line which is not enough to display one complete display line with true 8-bit resolution. Two methods of reducing data are available. One is simply skipping the 8-bit to 6-bit (SKIP6, I2C-bus bit) and the other is a small form of data reduction to come from 8-bit to 6-bit (SMART6, I2C-bus bit). If both bits are set to logic 0 the device is in true 8-bit resolution mode. For the twin PIP mode the main channel is not placed in the VDRAM but in an internal buffer, so still 8-bit resolution is achieved.
1996 Aug 13
10
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
Table 3 PIP modes PIP MODES NAME SP SP SP SP SP SP DP DP MP3L MR3R MR3D MP7 MP8 MP4 MP9 MP16 MP16 FFS FFL MAN FIGURE SP small SP medium SP large SP small SP medium SP large DP twin PIP POP-left POP-right POP-double POP-double MP7 Quatro MP9 MP16 MP16 mix full field still full field live manual MODE 0000 0000 0000 0000 0000 0000 0000 1001 0010 0010 0010 0011 0011 0001 0100 0101 0110 0000 1000 0111 SUB-CHANNEL REDH
1 1 1 4 3 2
SAB9076H
MAIN CHANNEL REDH - - -
1 1 1 1 1 1 1 1 1 1 1 1 4 3 2 2 2
SUB-CHANNEL HFP - - - - - - 03H 03H 08H - 08H 03H 03H 03H 03H 03H 03H 03H - X VFP - - - - - - 46H 05H 46H - 10H 05H 05H 05H 05H 05H 05H 05H - X
MAIN CHANNEL HFP - - - - - - 57H 57H - 72H 72H - 44H 03H 51H 03H 03H - 03H X VFP - - - - - - 46H 05H - 10H 10H - 20H 77H 3BH 05H 77H - 05H X
REDV
1 1 1 4 3 2
REDV - - -
1 1 1 1 1 1 1 1 1 1 1 1 4 3 2 2 1
- - -
1 1 1 1 1 1 1 1 1 1 1 2 2 4
- - -
1 1 1 1 1 1 1 1 1 1 1 2 1 4
-
4 4
-
4 4
-
4 4 4 2 3 4 4 1
-
4 4 4 2 3 4 4 1
-
2 2 3
-
2 2 3
-
4
-
4
-
1
-
1
- X
- X
X
X
PIP COMBINATIONS Figures 4, 5 and 6 provide an overview of possible combinations as they can be shown on the screen. An example of fine positioning is given in the right four columns of Table 3. More PIP modes can be obtained by varying the horizontal and vertical reduction factors to meet correct aspect ratios when using 16 : 9 screens.
1996 Aug 13
11
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
handbook, halfpage
handbook, halfpage
SP-Small
MGD594
SP-Medium
MGD595
handbook, halfpage
handbook, halfpage
SP-Large
MGD596
DP
MGD597
handbook, halfpage
handbook, halfpage
Twin-PIP
MGD598
POP-Left
MGD588
Fig.4 PIP Modes.
1996 Aug 13
12
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
handbook, halfpage
handbook, halfpage
POP-Right
MGD589
POP-Double
MGD590
handbook, halfpage
handbook, halfpage
MP7
MGD591
MP8
MGD592
handbook, halfpage
handbook, halfpage
MP13
MGD593
Quatro
MGD584
Fig.5 PIP Modes (continued).
1996 Aug 13
13
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
handbook, halfpage
handbook, halfpage
MP9
MGD585
MP16
MGD586
handbook, halfpage
Full Field Still Full Field Live
MGD587
Fig.6 PIP Modes (continued).
1996 Aug 13
14
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
I2C-bus description The I2C-bus provides bi-directional 2-line communication between different ICs. The SDA line is the serial data line and SCL serves as serial clock line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. The SAB9076H has the I2C-bus addresses 2C and 2E, switchable by the pin A0. Valid Sub-Addresses (SA) are 00H to 18H (Table 4) and 20H to 32H (Table 6). Table 4 SA BIT 7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H Note 1. The data bits which are not used should be set to zero. MPIPON note 1 DFILT BGHFP3 SDHFP7 SDVFP7 MDHFP7 MDVFP7 MDREDH1 MAREDH1 MAHFP3 SAVFP7 MAVFP7 MLSEL3 MBSEL3 BHSIZE3 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 BIT 6 SPIPON note 1 FILLOFF BGHFP2 SDHFP6 SDVFP6 MDHFP6 MDVFP6 MDREDH0 MAREDH0 MAHFP2 SAVFP6 MAVFP6 MLSEL2 MBSEL2 BHSIZE2 SBON SBSON MBON MBSON BGON note 1 note 1 FBDEL2 BIT 5 MFREEZE M1FLD SMART6 BGHFP1 SDHFP5 SDVFP5 MDHFP5 MDVFP5 MDREDV1 MAREDV1 MAHFP1 SAVFP5 MAVFP5 MLSEL1 MBSEL1 BHSIZE1 SBBRT1 SBSBRT1 MBBRT1 MBSBRT1 BGBRT1 note 1 note 1 FBDEL1 BIT 4 SFREEZE S1FLD SKIP6 BGHFP0 SDHFP4 SDVFP4 MDHFP4 MDVFP4 MDREDV0 MAREDV0 MAHFP0 SAVFP4 MAVFP4 MLSEL0 MBSEL0 BHSIZE0 SBBRT0 SBSBRT0 MBBRT0 MBSBRT0 BGBRT0 SVFILT MVFILT FBDEL0 BIT 3 note 1 YTH3 BGVFP3 SDHFP3 SDVFP3 MDHFP3 MDVFP3 SDREDH1 SAREDH1 SAHFP3 SAVFP3 MAVFP3 SLSEL3 SBSEL3 BVSIZE3 note 1 note 1 note 1 note 1 note 1 SUVPOL MUVPOL DUVPOL BIT 2 DNONINT YTH2 BGVFP2 SDHFP2 SDVFP2 MDHFP2 MDVFP2 SDREDH0 SAREDH0 SAHFP2 SAVFP2 MAVFP2 SLSEL2 SBSEL2 BVSIZE2 SBCOL2 SBSCOL2 MBCOL2 MBSCOL2 SBGCOL2 SVSPOL MVSPOL DVSPOL Overview of I2C-bus sub-addresses DATA BYTE
SAB9076H
I2C-bus control is in accordance with the I2C-bus protocol. First a START sequence must be put on the I2C-bus, then the I2C-bus address of the circuit must be send, followed by a subaddress. After this sequence the data of the subaddresses must be sent. An auto-increment function gives the option to send data of the incremented subaddresses until a STOP sequence is send. Table 4 gives an overview of the I2C-bus addresses.
BIT 1 MNONINT YTH1 BGVFP1 SDHFP1 SDVFP1 MDHFP1 MDVFP1 SDREDV1 SAREDV1 SAHFP1 SAVFP1 MAVFP1 SLSEL1 SBSEL1 BVSIZE1 SBCOL1 SBSCOL1 MBCOL1 MBSCOL1 SBGCOL1 SHSYNC MHSYNC DHSYNC
BIT 0 SNONINT YTH0 BGVFP0 SDHFP0 SDVFP0 MDHFP0 MDVFP0 SDREDV0 SAREDV0 SAHFP0 SAVFP0 MAVFP0 SLSEL0 SBSEL0 BVSIZE0 SBCOL0 SBSCOL0 MBCOL0 MBSCOL0 SBGCOL0 SFPOL MFPOL DFPOL
PIPMODE3 PIPMODE2 PIPMODE1 PIPMODE0
PEDESTV3 PEDESTV2 PEDESTV1 PEDESTV0 PEDESTU3 PEDESTU2 PEDESTU1 PEDESTU0
1996 Aug 13
15
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SA 00H PIP REGISTER The MPIPON and SPIPON bits switch respectively the main and sub PIPs of the SAB9076H on or off. The MFREEZE and SFREEZE bits make the current live pictures for the channels main and sub frozen. The writing to the VDRAM is stopped. The PIPMODE3 to PIPMODE0 bits set the PIP mode in accordance with Table 3. SA 01H DISPLAY REGISTER The M1FLD and S1FLD(1) bits control the use of the reserved second field in the VDRAM. If this bit is set to logic 0 then address spaces are reserved for both fields in the VDRAM. This avoids joint line errors. Whether these address spaces are used is dependent on the interlacing of the input signals and the three NONINT bits. If a 1FLD bit is set to logic 1 then only 1 address space is used in the VDRAM for both fields. In some PIP modes the use of a second field is not possible since there is not enough space in the VDRAM, in these modes the 1FLD bit must be set to logic 1. DNONINT controls the interlace mode of the display part. If set to logic 1 then data is only read from one field in the VDRAM. If set to logic 0 then both fields (if available) are used for display. The MNONINT and SNONINT bits control the interlace mode of the acquisition blocks. If set to logic 1 then data is only written to one field in the VDRAM (two fields remain allocated). If set to logic 0 then both fields (if available) are used for acquisition. SA 02H DISPLAY REGISTER The DFILT bit controls an interpolating filter that changes the internal 864 pixels data rate to the output data rate of 2 x 864 pixels. If DFILT is set to logic 1 then the filter is on. The FILLOFF bit controls filling of PIPs when the PIP mode is switched. If FILLOFF is set to logic 0 then all PIPs are filled with a 30% gray until their channel has been updated. If FILLOFF is set to logic 1 then the VDRAM content is always visible. This is useful when a new, `similar' to the previous one, PIP mode is set. The previous data can then be displayed. The SMART6 and SKIP6 bits control the data transfer mode to the external VDRAM. For modes which display a complete line (672 pixels) a type of data reduction has to be carried out. Two transfer modes are available. One is simply skipping the 8-bit data path to 6-bit (SKIP6). The other is carry out an intelligent data reduction which retains an 8-bit resolution (SMART6).
(1) The 1 FLD bits only operate when the NONINT bits of the corresponding channel is set.
SAB9076H
The YTH3 to YTH0 bits control the video output. If the current Y-value is less then YTH x 16 then the fast blank is switched off, the original live background will be visible. This feature can be used to pick up sub-titles and display them as On-Screen Display (OSD) anywhere on the screen. SA 03H DISPLAY BACKGROUND FINE POSITIONING REGISTER The BGHFP3 to BGHFP0 bits control the horizontal display positioning of the background. The resolution is 16 steps of 4 pixels. The BGVFP3 to BGVFP0 bits control the vertical display positioning of the background. The resolution is 16 steps of 2 lines/field. The background fine positioning moves the complete display. It is a general offset of all the PIP pictures and background. It is intended only to adjust once the centring of all PIP modes (see Fig.3). SA 04H AND SA 05H DISPLAY SUB-CHANNEL FINE
POSITIONING REGISTERS
These registers control the horizontal and vertical fine positioning of the display sub-channel with respect to the display background. This is the actual fine positioning (see Fig.3). The horizontal resolution is 256 steps of 4 pixels and the vertical resolution is 256 steps of 1 line/field. SA 06H AND SA 07H DISPLAY MAIN-CHANNEL FINE
POSITIONING REGISTERS
These registers control the horizontal and vertical fine positioning off the display main-channel with respect to the display background. This is the actual fine positioning (see Fig.3). The horizontal resolution is 256 steps of 4 pixels and the vertical resolution is 256 steps of 1 line/field. SA 08H DISPLAY REDUCTION FACTORS REGISTER This register sets the display reduction factors, independent of the acquisition reduction factors. It sets the PIP size to a certain default value in such a way that the border drawn around the PIP is just fitting. SA 09H ACQUISITION REDUCTION FACTORS REGISTER This register sets the acquisition reduction factors, independent of the display reduction factors. If the HRED is 1 : 1 then the VRED must also be 1 : 1. Restrictions are: * The DREDH and AREDH must be the same * The DREDV is equal or smaller than the AREDV (e.g DREDV is 1 : 2 and AREDV is 1 : 1).
1996 Aug 13
16
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SA 0AH TO SA 0CH ACQUISITION FINE POSITIONING
REGISTERS
SAB9076H
If SBSON is set to logic 1 then one sub-PIP border can have a different colour. This border is selected by the SBSEL3 to SBSEL0 bits. The SBSBRT and SBSCOL bits control the brightness and colour off the sub-border selection colour. SA 12H AND SA 13H BORDER COLOUR AND BORDER
These registers determine the start of the acquisition area. Horizontal fine positioning can be adjusted with 16 steps of 2 pixels, vertical fine positioning can be adjusted with 256 steps of 1 line/field. SA 0DH TO SA 0EH SELECTION REGISTERS The MLSEL3 to MLSEL0 and SLSEL3 to SLSEL0 bits control which PIP is live. Both main channel and sub-channel can have one live PIP. Counting is carried out from upper-left to lower-right. The MBSEL3 to MBSEL0 and SBSEL3 to SBSEL0 bits control which PIP border has a different colour. Both main channel and sub-channel can have a different PIP channel border selection. Counting is done from upper-left to lower-right. SA 0FH BORDER SIZE REGISTER This register controls the border size. The minimum horizontal border is 2 pixels. The minimum vertical border is 1 line. The vertical border size is multiplied by the FH mode number before it is displayed on the screen. SA 10H AND SA 11H BORDER COLOUR AND BORDER SELECT (see Table 5) If SBON is set to logic 1 then the border of the sub-channel is visible. SBBRT and SBCOL control the brightness and colour of the sub-channel border colour.
SELECTION COLOUR OF MAIN CHANNEL REGISTERS
(see Table 5) If MBON is set to logic 1 then the border of the main channel is visible. The MBBRT and MBCOL bits control the brightness and colour of the main-channel border colour. If MBSON is set to logic 1 then one main PIP border can have a different colour. This border is selected by the MBSEL3 to MBSEL0 bits. The MBSBRT and MBSCOL bits control the brightness and colour off the main-border selection colour. SA 14H BACKGROUND CONTROL REGISTER (see Table 5) If BGON is set to logic 1 then the background is visible. BGBRT and BGCOL registers control the brightness and colour of the background colour.
COLOUR OF SUB-CHANNEL REGISTERS
1996 Aug 13
17
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
Table 5 Colour types and brightness levels COLOUR TYPE COLOUR Black Blue Red Magenta Green Cyan Yellow White VALUE 0H 1H 2H 3H 4H 5H 6H 7H 4H 0% 30% 30% 30% 30% 30% 30% 60% BRIGHTNESS LEVEL 5H 10% 50% 50% 50% 50% 50% 50% 70% 6H 30% 70% 70% 70% 70% 70% 70% 80%
SAB9076H
7H 50% 100% 100% 100% 100% 100% 100% 100%
Table 5 indicates how I2C-bus register settings control the colour and brightness. All colour registers are similar, they contain one on/off bit, two brightness bits and three colour type bits. To determine which colour is visible in the event two or more colours being displayed on the same position, the next priority scheme is followed. 1. Sub-select colour (SBS) 2. Sub-border colour (SB) 3. Main-select colour (MBS) 4. Main-border colour (MB) 5. Background colour (BG). SA 15H AND SA 16H DECODER REGISTERS The MVFILT and SVFILT bits can set the type of vertical filtering. The MUVPOL and SUVPOL bits invert the UV polarity of the incoming signals. The MVSPOL and SVSPOL bits determine the active edge of the Vsync (see Fig.7). MHSYNC and SHSYNC bits determine the timing of the Hsync pulse (burstkey or Hsync timing). The MFPOL and SFPOL bits can invert the field identification (ID) of the incoming fields (see Fig.7).
SA 17H DISPLAY SETTINGS REGISTER The FBDEL2 to FBDEL0 bits can adjust the fast blank delay in 8 steps of 12 a clock cycle (-8 to +7). 0H is mid-scale. The DUVPOL bit inverts the UV polarity of the border colours. The DVSPOL bit determines the active edge of the Vsync (see Fig.7). The DHSYNC bit determines the timing of the Hsync pulse (burstkey or Hsync). The DFPOL bit can invert the field identification of the incoming fields (see Fig.7). SA 18H PEDESTAL SETTINGS REGISTER The PEDESTU3 to PEDESTU0 and PEDESTV3 to PEDESTV0 bits provide the U and V DAC outputs an offset of -8 to +7 LSB when the FBL is switched off. This can be used to adjust the white point of the system.
1996 Aug 13
18
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
Additional I2C-bus settings Table 6 SA BIT 7 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H Note 1. The data bits which are not used should be set to zero. In Manual mode more PIP modes become available with the help of register 20H to 32H. An overview of these I2C-bus registers is given in Table 6. The meaning and relation of the I2C-bus registers is shown in Fig.8. The background has a fixed size and can be fine positioned with the BGHFP and BGHFP bits. The shown PIPs are only for one channel (Main or Sub), the other channel has the same control and can be displayed at the same time. The SDHFP and MDHFP bits determine the most left shown pixel for this channel in 256 steps of 4 pixels. The SDVFP and MDVFP bits determine the most upper shown line for this channel in 256 steps of 1 line. The SHPIC and MHPIC bits determine the horizontal picture size in 256 steps of 4 pixels, the minimum value is 4 pixels. The SVPIC and MVPIC bits determine the vertical picture size in 256 steps of 1 line, the minimum value is 1 line. The PIP mode is built-up of a maximum of four horizontal rows. The minimum is one row, more rows can 1996 Aug 13 19 PRIO MHRPO31 MHRPN31 MHPIC7 MVPIC7 MHDIS07 MHDIS17 MHDIS27 MHDIS37 MVDIS7 SHRPO31 SHRPN31 SHPIC7 SVPIC7 SHDIS07 SHDIS17 SHDIS27 SHDIS37 SVDIS7 BIT 6 note 1 MHRPO30 MHRPN30 MHPIC6 MVPIC6 MHDIS06 MHDIS16 MHDIS26 MHDIS36 MVDIS6 SHRPO30 SHRPN30 SHPIC6 SVPIC6 SHDIS06 SHDIS16 SHDIS26 SHDIS36 SVDIS6 BIT 5 note 1 MHRPO21 MHRPN21 MHPIC5 MVPIC5 MHDIS05 MHDIS15 MHDIS25 MHDIS35 MVDIS5 SHRPO21 SHRPN21 SHPIC5 SVPIC5 SHDIS05 SHDIS15 SHDIS25 SHDIS35 SVDIS5 BIT 4 note 1 MHRPO20 MHRPN20 MHPIC4 MVPIC4 MHDIS04 MHDIS14 MHDIS24 MHDIS34 MVDIS4 SHRPO20 SHRPN20 SHPIC4 SVPIC4 SHDIS04 SHDIS14 SHDIS24 SHDIS34 SVDIS4 BIT 3 MVRPN1 MHRPO11 MHRPN11 MHPIC3 MVPIC3 MHDIS03 MHDIS13 MHDIS23 MHDIS33 MVDIS3 SHRPO11 SHRPN11 SHPIC3 SVPIC3 SHDIS03 SHDIS13 SHDIS23 SHDIS33 SVDIS3 BIT 2 MVRPN0 MHRPO10 MHRPN10 MHPIC2 MVPIC2 MHDIS02 MHDIS12 MHDIS22 MHDIS32 MVDIS2 SHRPO10 SHRPN10 SHPIC2 SVPIC2 SHDIS02 SHDIS12 SHDIS22 SHDIS32 SVDIS2 Overview of additional I2C-bus sub-addresses DATA BYTE
SAB9076H
BIT 1 SVRPN1 MHRPO01 MHRPN01 MHPIC1 MVPIC1 MHDIS01 MHDIS11 MHDIS21 MHDIS31 MVDIS1 SHRPO01 SHRPN01 SHPIC1 SVPIC1 SHDIS01 SHDIS11 SHDIS21 SHDIS31 SVDIS1
BIT 0 SVRPN0 MHRPO00 MHRPN00 MHPIC0 MVPIC0 MHDIS00 MHDIS10 MHDIS20 MHDIS30 MVDIS0 SHRPO00 SHRPN00 SHPIC0 SVPIC0 SHDIS00 SHDIS10 SHDIS20 SHDIS30 SVDIS0
be displayed by setting the Vertical Repetition Rate Number VRPN bits. The distance between the rows can be set by SVDIS and MVDIS bits. Every row is built-up of a maximum of four PIPs. The minimum is one PIP and the distance between the starting points of those PIPs on a row is determined by SHDIS and MHDIS bits. SA 20H CONTROL REGISTER The PRIO bit sets the priority between Main and Sub channel. If PRIO is set to logic 0, priority is given to the Sub channel which means that the Sub channel PIPs, if present, are placed on top of the Main PIPs. If PRIO is set to logic 1, the Main PIPs are set on top of the Sub PIPs. The MVRPN and SVRPN bits determine the number of repeated PIP rows. There is always one row visible of each channel. If no PIPs should be visible the PIP channel must be switched off (SA 00, bit 7 or bit 6).
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SA 21H AND SA 2AH HORIZONTAL REPETITION OFFSET REGISTERS FOR ROW 0 TO 3 The horizontal repetition offsets (MHRPO and SHRPO bits) are strongly related to the horizontal distance (MHDIS and SHDIS bits). These registers set for each row a certain grid of possible starting points for the PIPS in that row. Every grid point has a number 0 (the most left PIP), 1, 2 or 3. The MHRPO and SHRPO bits determine the first PIP number which will be displayed. This mechanism can be set for each row. SA 22H AND SA 2BH HORIZONTAL REPETITION NUMBER REGISTERS FOR ROW 0 TO 3 The horizontal repetition numbers (MHRPN and SHRPN bits) determine how many times the PIPs are repeated in a row, once the first PIP is displayed. The repeated PIPs stay in the grid determined by the MHDIS and SHDIS bits for that row. This mechanism can be set for each row independent. SA 23H AND SA 24H; SA 2CH AND SA 2DH PICTURE SIZE
REGISTERS
SAB9076H
The reference levels are made internally by a resistor network which divides the analog supply voltage to a default set of preferred levels. External capacitors are needed to filter AC components on the reference levels. The resolution of the ADCs is 8 bit. Differential Non-Linearity (DNL) is 7-bit; Integral Non-Linearity (INL) is 6-bit, and the sampling is carried out at the system frequency of 27 MHz for the Y input. The U/V inputs are multiplexed and sampled at 13.5 MHz. The analog input signals are amplified to make maximum use of the dynamic range of the ADCs. A bias voltage Vbias is used for decoupling AC components on internal references. The inputs should be AC-coupled and an internal clamping circuit will clamp the input to AVrefB for the luminance AV refT - AV refB LSB channels and to ---------------------------------------- + ----------- for the 2 2 chrominance channels. The clamping starts at the active edge of the burst key. Output DACs The digitally processed signals are converted to analog signals by three 8-bit DACs. The output voltages of these DACs are default set by the DAVrefT pin for the top level and DAVrefB pin for the bottom level. Default values are 1.5 V. External Memory For the external memory two VDRAMs of type Mitsubishi M5M442256 are used. They have a storage capacity of 262 144 words of 4-bit each and will be used in parallel. It is also possible to use a 2 Mbit VDRAM with a storage capacity of 262 144 words of 8 bit each. An overview of the timing diagrams is given in Fig.9.
The MHPIC and SHPIC bits determine the horizontal PIP size in 256 steps of 4 pixels. The MVPIC and SVPIC bits determine the vertical PIP size in 256 steps of 1 line. SA 25H AND SA 29H; SA 2EH AND SA 32H PICTURE DISTANCE REGISTERS For each row the distance between starting points of PIPs can be set with the bits MHDIS and SHDIS in 256 steps of 4 pixels. The distance between two rows can be set with the MVDIS and SVDIS bits in 256 steps of 1 line. Acquisition Channel ADCs Both channels convert the analog input signals to digital signals by means of two ADCs for each channel. The input levels of the ADCs of each channel are equal and can be set by the AVrefT and AVrefB pins.
1996 Aug 13
20
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
handbook, full pagewidth H (external)
sync
field ID (internal) (number of pixels) 43 V sync (external) 1st field V sync (external)
MBE100
389
432
2nd field
Fig.7 Vertical synchronization timing and field identification.
handbook, full pagewidth
BGHFP
BGVFP
DVFP DHFP 1 + VRPN rows VPIC HPIC
VDIS
HDIS 1 + HRPN columns
MGD583
Fig.8 Relation of display I2C-bus register.
1996 Aug 13
21
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
(1) handbook, full pagewidth CLOCK
RAS
CAS refresh cycle
CLOCK
(2)
RAS
CAS
AD0 to AD8
ROW
COLUMN
COLUMN
COLUMN
COLUMN
COLUMN
WE
DAO0 to DAO7 write cycle (main or sub)
CLOCK
(2)
RAS
CAS
AD0 to AD8
ROW
COLUMN
WE
DT read cycle
SC
DAI0 to DAI7 (1) CLOCK = 13.5 MHz. (2) CLOCK = 27 MHz.
MGC970
shift clock cycles
Fig.9 VDRAM timing
1996 Aug 13
22
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Pmax Tstg Tamb Vesd supply voltage maximum power dissipation storage temperature operating ambient temperature electrostatic discharge handling Human body model Machine model Note 3000(1) 300(2) PARAMETER -0.5 - -25 -25 MIN. +6.5 1.5 +150 +70 MAX.
SAB9076H
UNIT V W C C V V
1. Human body model: see UZW-B0/FQ-B302; The numbers of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192. 2. Machine model: see UZW-B0/FQ-A302; The numbers of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 34 UNIT K/W
QUALITY SPECIFICATION In accordance with "SNW-FQ-611 part E". The numbers of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192.
1996 Aug 13
23
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
CHARACTERISTICS VDD = 5.0 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supply VDD VSS VDD(max) VSS(max) IDDDQ IMPVDDA ISPVDDA IDPVDDA IMAVDDA ISAVDDA IDAVDDA IDDA(tot) IDDD(tot) VrefT VrefB Ii Ci fs RES DNL INL cs PSRR VclampY VclampUV all positive supply voltages all ground voltages maximum difference between supply voltages maximum difference between ground voltages quiescent current of digital supply voltages main PLL supply current sub PLL supply current display PLL supply current main ADCs supply current sub ADCs supply current display DACs supply current total analog supply current total digital supply current note 1 4.5 - - - - - - - - - - - - 5.0 0 0 0 0 6 6 6 40 40 20 115 100 PARAMETER CONDITIONS MIN. TYP.
SAB9076H
MAX.
UNIT
5.5 - 100 100 50 - - - - - - - -
V V mV mV A mA mA mA mA mA mA mA mA
Analog-to-digital converter and clamping top reference voltage bottom reference voltage input current input capacitance sample frequency rate resolution differential non-linearity integral non-linearity channel separation power supply rejection ratio clamping voltage level Y clamping voltage level U/V note 4 note 3 note 2 note 2 note 2 clamping off clamping on 1.9 0.3 1.2 - - - - 6 -2.0 -4.0 - - - - 2.1 0.4 1.5 0.1 100 5 1728HS 8 - - 48 48 VrefB note 5 2.3 0.5 1.6 - - - - - +2.0 +4.0 - - - - V V V A A pF MHz bit LSB LSB dB dB V V
Vi(Y,U,V)(p-p) input signal amplitude (peak-to peak value)
1996 Aug 13
24
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital-to-analog converter and output stage VrefT VrefB Vo(Y,U,V) RL CL fs RES DNL INL cs PSRR top reference voltage bottom reference voltage output signal amplitude load resistance load capacitance sample frequency rate resolution differential non-linearity integral non-linearity channel separation power supply rejection ratio note 3 note 6 note 6 2.2 0.3 - 75 0 - 6 -1.0 -1.0 - - 2.3 0.4 1.5 220 - 1728HS 8 - - 48 48 2.4 0.5 1.6 10 x 50 - 8 +1.0 +1.0 - - 103 V V V pF MHz bit LSB LSB dB dB
PLL and clock generation acquisition fi(PLL) fi(PLL) Notes 1. Digital clocks are silent, POR is VDD. 2. The VrefT and VrefB are made by a resistor division of the VDD. They can be calculated with the formulas: 2.0 0.4 V refT = AV DD x ------- V and V refB = AV DD x ------- V 5.0 5.0 The analogue supply voltages are 5 V. 3. The internal system frequency is 1728 times the Hsync input frequency for both the acquisition and display PLLs. 4. The Y-channel is clamped to the VrefB of the ADCs. 5. The UV-channel is clamped to 1/2(VrefT + VrefB + VLSB). 6. The gain of the SAB9076H is 1 under the condition that the RL is 220 . input frequency note 3 14 15.75 18 kHz
PLL and clock generation display input frequency note 3 14 15.75 18 kHz
1996 Aug 13
25
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
DC CHARACTERISTICS FOR THE DIGITAL PART VDDD = 4.5 to 5.5 V (all VDDD pins); Tamb = -20 to +75 C; unless otherwise specified. SYMBOL VIH PARAMETER HIGH level input voltage HPF01 HPP01 HUP07 IOI41 VIL LOW level input voltage HPF01 HPP01 HUP07 IOI41 Vhys VOH VOL ILI IOZ Rpu Note 1. Vi is attached to the VDDD or VSSD. AC CHARACTERISTICS FOR THE DIGITAL PART VDDD = 4.5 to 5.5 V (all VDDD pins); Tamb = -20 to +75 C; unless otherwise specified. SYMBOL fsys tr tf Note PARAMETER system frequency rise time fall time CONDITIONS acquisition; note 1 display; note 1 - - - - MIN. TYP. 27 27 6 6 hysteresis voltage HIGH level output voltage LOW level output voltage input leakage current HUP07 OPF20; IOL = -2 mA; VDDD = 4.5 V IOI41; IOL = +4 mA; VDDD = 4.5 V OPF20; IOL = +2 mA; VDDD = 4.5 V HPF01; VDDD = 5.5 V; note 1 HPP01; VDDD = 5.5 V; note 1 3-state output leakage current IOI41; VDDD = 5.5 V; note 1 internal pull-up resistor HUP07 CONDITIONS MIN. 70 70 80 70 - - - - - 4.1 - - - - - 17 - - - - - - - - 33 - - - 0.1 0.1 0.2 - TYP.
SAB9076H
MAX. - - - - 30 30 20 30 - - 0.4 0.4 1 1 5 134
UNIT %VDD %VDD %VDD %VDD %VDD %VDD %VDD %VDD %VDD V V V A A A k
MAX. 30 30 25 25
UNIT MHz MHz ns ns
1. The internal system frequency is1728 times the Hsync input frequency for both the acquisition and display PLLs.
1996 Aug 13
26
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
TEST AND APPLICATION INFORMATION The application diagram for 1 FH mode in a standard configuration is shown in Fig.10. Two input signals MCVBS and SCVBS of different sources are processed by the SAB9076H and inserted by the YUV/RGB switch.
SAB9076H
The synchronization of the display PLL is derived from the deflection circuit. The main signals are also fed to the deflection circuit and the YUV/RGB switch where the SAB9076H signals can be inserted. The signals for deflection can also be taken from the main channel or sub-channel decoder.
handbook, full pagewidth
VDRAM 2 Mbit
HS VS SCVBS DECODER SUB
Y U V SAB9076H HS VS FLB HS (1 FH) VS YUV/RGB SWITCH AND DEFLECTION CIRCUIT R YUV TO RGB G B R G HS VS B HS VS
MCVBS
DECODER MAIN
Y U V
Y U V
main signals
Y U V
MGC971
Fig.10 Application diagram for 1 FH mode.
1996 Aug 13
27
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SAB9076H
+5 V
handbook, full pagewidth
+5 V 95 DPHsync 94 93 91 DAVSSD DFB 92 90 DAVDDD DU 89 88 87 86 85 84 DAVrefB DAVrefT DV DY DAVbias DAVSSA
+5 V 83 DAVDDA
97 DPVSSA
98 96 DPVDDA DPVbias
DVsync
1 +5 V 99 100 +5 V 4 3 2 HOUT VOUT 17
MPVbias MPVDDA MPVSSA MAVDDD MAVSSD MPHsync
80 SPVbias 82 SPVDDA SPVSSA 77 SAVDDD SAVSSD SPHsync SVsync 76 SAVbias 73 SV 72 SAVrefB 75 SU 74 SAVrefT 71 SY 70 SAVDDA 69 SAVSSA 67 SVDDD 68 SVSSD 66 SCVDDD SCVSSD POR SDA SCL AD0 to AD8 A0 VDDD VSSD 65 62 61 60 59 64 78 79 81
+5 V
+5 V
HOUT VOUT
-V
TDA8315T
-U
Y CVBS/Y +5 V
MVsync 5 MAVbias 8 MV 9 MAVrefB 6 MU 7 MAVrefT 10 MY 11 MAVDDA 12 MAVSSA MVDDD MVSSD MCVDDD MCVSSD TDCLK TACLK TC TM0 TM1 DAO0 to DAO7 DAI0 to DAI7 n.c.
-V
TDA8315T
-U
SAB9076H
Y +5 V CVBS/Y
CVBS/Y main-channel input
+5 V
14 13
+5 V
CVBS/Y sub-channel input
+5 V
15 16 18 63 19 20 21 22
+5 V
CAS
RAS
WE
SC
DT
DCVDDD
DCVSSD
DVDDD
DVSSD
8
32, 34, 36, 38, 8 39, 37, 35, 33
43 23, 25, 40 31 47 48 49 51, 53, 44 27, 29, 9 55, 57, 58, 56, 30, 28, 54, 52, 26, 24 +5 V 50 2 Mbit MEMORY
41
42
45
46
+5 V
+5 V
MGC972
All capacitors are 100 nF. On the application board a ground plane should be used.
Fig.11 Application diagram.
1996 Aug 13
28
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAB9076H
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
wM pin 1 index bp 100 1 wM D HD ZD B vM B 30 vMA 31
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Aug 13
29
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
SAB9076H
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Aug 13
30
Philips Semiconductors
Preliminary specification
Picture-In-Picture (PIP) controller
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAB9076H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Aug 13
31
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 615 800, Fax. +358 615 80920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. +30 1 4894 339/911, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/50/01/pp32
Date of release: 1996 Aug 13
Document order number:
9397 750 01016

▲Up To Search▲

Price & Availability of SAB9076H

	To Download SAB9076H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .